ST STM32G4 Series Reference Manual page 1161

RM0440
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:0 CCR3[19:0]: Capture/compare value
If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual
capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on tim_oc3 output.
Non-dithering mode (DITHEN = 0)
The register holds the compare value in CCR3[15:0]. The CCR3[19:16] bits are reset.
Dithering mode (DITHEN = 1)
The register holds the integer part in CCR3[19:4]. The CCR3[3:0] bitfield contains the
dithered part.
If channel CC3 is configured as input: CCR3 is the counter value transferred by the last
input capture 3 event (tim_ic3). The TIMx_CCR3 register is read-only and cannot be
programmed.
Non-dithering mode (DITHEN = 0)
The register holds the capture value in CCR3[15:0]. The CCR3[19:16] bits are reset.
Dithering mode (DITHEN = 1)
The register holds the capture in CCR3[19:4]. The CCR3[3:0] bits are reset.
27.6.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 1, 8, 20)
Address offset: 0x040
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
Advanced-control timers (TIM1/TIM8/TIM20)
24 23 22
Res. Res. Res.
8 7 6
CCR4[15:0]
rw rw rw
RM0440 Rev 1
21 20 19 18
Res. Res. CCR4[19:16]
rw rw
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
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