ST STM32G4 Series Reference Manual page 1289

RM0440
Bits 31:0 CCR4[31:0]: Capture/compare 4 value
28.5.25 TIMx timer encoder control register (TIMx_ECR)(x = 2 to 5)
Address offset: 0x058
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:24 PWPRSC[2:0]: Pulse width prescaler
This bitfield sets the clock prescaler for the pulse generator, as following:
t
PWG
Bits 23:16 PW[7:0]: Pulse width
t
PW
Bits 15:8 Reserved, must be kept at reset value.
If channel CC4 is configured as output:
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is
loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit
OC4PE). Else the preload value is copied in the active capture/compare 4 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on tim_oc4 output.
Non-dithering mode (DITHEN = 0)
The register holds the compare value.
Dithering mode (DITHEN = 1)
The register holds the integer part in CCR4[31:4]. The CCR4[3:0] bitfield contains the
dithered part.
If channel CC4 is configured as input:
CCR4 is the counter value transferred by the last input capture 4 event (tim_ic4). The
TIMx_CCR4 register is read-only and cannot be programmed.
Non-dithering mode (DITHEN = 0)
The register holds the capture value.
Dithering mode (DITHEN = 1)
The register holds the capture in CCR4[31:0]. The CCR4[3:0] bits are reset.
28 27 26 25
Res. PWPRSC[2:0]
rw rw
12 11 10 9
Res. Res. Res.
(PWPRSC[2:0])
= (2 ) x
This bitfield defines the pulse duration, as following:
= PW[7:0] x t
PWG
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
24 23 22
rw rw rw
8 7 6
Res. IPOS[1:0]
rw rw
t
tim_ker_ck
RM0440 Rev 1
21 20 19 18
PW[7:0]
rw rw rw rw
5 4 3 2
FIDX Res. Res.
rw rw
17 16
rw rw
1 0
IDIR[1:0] IE
rw rw
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