ST STM32G4 Series Reference Manual page 1131

RM0440
27.6 TIM1/TIM8/TIM20 registers
Refer to
27.6.1 TIMx control register 1 (TIMx_CR1)(x = 1, 8, 20)
Address offset: 0x000
Reset value: 0x0000
15 14 13
DITH
Res. Res. Res.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 DITHEN: Dithering enable
Note: The DITHEN bit can only be modified when CEN bit is reset.
Bit 11 UIFREMAP: UIF status bit remapping
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
Bit 7 ARPE: Auto-reload preload enable
Bits 6:5 CMS[1:0]: Center-aligned mode selection
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
Section 1.2 for a list of abbreviations used in register descriptions.
12 11 10 9
UIFRE
Res. CKD[1:0]
EN MAP
rw rw rw
0: Dithering disabled
1: Dithering enabled
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and
the dead-time and sampling clock (t
filters (tim_etr_in, tim_tix),
00: t =t
DTS tim_ker_ck
01: t =2*t
DTS tim_ker_ck
10: t =4*t
DTS tim_ker_ck
11: Reserved, do not program this value
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
the counter is enabled (CEN=1)
Advanced-control timers (TIM1/TIM8/TIM20)
8 7 6
ARPE CMS[1:0]
rw rw rw
)used by the dead-time generators and the digital
DTS
RM0440 Rev 1
5 4 3 2
DIR OPM URS
rw rw rw rw
1 0
UDIS CEN
rw rw
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