ST STM32G4 Series Reference Manual page 1383

Advanced arm-based 32-bit mcus

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TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17)

Address offset: 0x20

Reset value: 0x0000

Bits 15:4 Reserved, must be kept at reset value.

Bit 3 CC1NP: Capture/Compare 1 complementary output polarity

CC1 channel configured as output:

CC1 channel configured as input:

Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK

0: tim_oc1n active high

1: tim_oc1n active low

This bit is used in conjunction with CC1P to define the polarity of tim_ti1fp1. Refer to the

description of CC1P.

bits in TIMx_BDTR register) and CC1S="00" (the channel is configured in output).

2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit

is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the

preloaded bit only when a commutation event is generated.

General-purpose timers (TIM15/TIM16/TIM17)

RM0440 Rev 1

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