ST STM32G4 Series Reference Manual page 1134

Advanced-control timers (TIM1/TIM8/TIM20)
Bit 12 OIS3: Output idle state 3 (tim_oc3n output)
Refer to OIS1 bit
Bit 11 OIS2N: Output idle state 2 (tim_oc2n output)
Refer to OIS1N bit
Bit 10 OIS2: Output idle state 2 (tim_oc2 output)
Refer to OIS1 bit
Bit 9 OIS1N: Output idle state 1 (tim_oc1n output)
0: tim_oc1n=0 after a dead-time when MOE=0
1: tim_oc1n=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
Bit 8 OIS1: Output idle state 1 (tim_oc1 output)
0: tim_oc1=0 (after a dead-time) when MOE=0
1: tim_oc1=1 (after a dead-time) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
Bit 7 TI1S: tim_ti1 selection
0: The tim_ti1_in[15..0] multiplexer output is connected to tim_ti1 input
1: tim_ti1_in[15..0], tim_ti2_in[15..0] and tim_ti3_in[15..0] multiplexers outputs are XORed
Bits 6:4 MMS[2:0]: Master mode selection
These bits, together with the MMS[3] bit, allow to select the information to be sent in master
mode to slave timers for synchronization (tim_trgo). The combination is as follows:
0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If
the reset is generated by the trigger input (slave mode controller configured in reset mode)
then the signal on tim_trgo is delayed compared to the actual reset.
0001: Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enable. The Counter Enable signal is generated by a logic AND between CEN control bit
and the trigger input when configured in gated mode. When the Counter Enable signal is
controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode
is selected (see the MSM bit description in TIMx_SMCR register).
0010: Update - The update event is selected as trigger output (tim_trgo). For instance a
master timer can then be used as a prescaler for a slave timer.
0011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to
be set (even if it was already high), as soon as a capture or a compare match occurred.
(tim_trgo).
0100: Compare - tim_oc1ref signal is used as trigger output (tim_trgo)
0101: Compare - tim_oc2ref signal is used as trigger output (tim_trgo)
0110: Compare - tim_oc3ref signal is used as trigger output (tim_trgo)
0111: Compare - tim_oc4ref signal is used as trigger output (tim_trgo)
1000: Encoder Clock output - The encoder clock signal is used as trigger output (tim_trgo).
This code is valid for the following SMS[3:0] values: 0001, 0010, 0011, 1010, 1011, 1100,
1101, 1110, 1111. Any other SMS[3:0] code is not allowed and may lead to unexpected
behavior.
Other codes reserved
Note: The clock of the slave timer or ADC must be enabled prior to receive events from the
1134/2083
(LOCK bits in TIMx_BDTR register).
(LOCK bits in TIMx_BDTR register).
and connected to the tim_ti1 input
master timer, and must not be changed on-the-fly while triggers are received from the
master timer.
RM0440 Rev 1
RM0440