ST STM32G4 Series Reference Manual page 1021

RM0440
26.5.76 HRTIM ADC extended trigger register (HRTIM_ADCER)
Address offset: 0x3F8
Reset value: 0x0000 0000
31 30 29
Res. ADC10TRG[4:0]
rw rw
15 14 13
Res. ADC7TRG[4:0]
rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:26 ADC10TRG[4:0]: ADC trigger 10 selection
This bit selects the ADC trigger 10 source.
Refer to ADC6TRG[4:0] description.
Bits 25:21 ADC9TRG[4:0]: ADC trigger 9 selection
This bit selects the ADC trigger 9 source.
Refer to ADC5TRG[4:0] description.
Bits 20:16 ADC8TRG[4:0]: ADC trigger 8 selection
This bit selects the ADC trigger 8 source.
Refer to ADC6TRG[4:0] description.
Bit 15 Reserved, must be kept at reset value.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
24 23 22
ADC9TRG[4:0]
rw rw rw
8 7 6
ADC6TRG[4:0]
rw rw rw
RM0440 Rev 1
High-resolution timer (HRTIM)
21 20 19 18
ADC8TRG[4:0]
rw rw rw rw
5 4 3 2
ADC5TRG[4:0]
rw rw rw rw
17 16
rw rw
1 0
rw rw
1021/2083
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