User Manuals: ST STM32G071GB ARM Cortex-M0+ MCU
Manuals and User Guides for ST STM32G071GB ARM Cortex-M0+ MCU. We have 1 ST STM32G071GB ARM Cortex-M0+ MCU manual available for free PDF download: Reference Manual
ST STM32G071GB Reference Manual (1390 pages)
Brand: ST
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Category: Microcontrollers
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Size: 17 MB
Table of Contents
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Glossary54
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Introduction58
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FLASH Registers100
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Table 10108
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Power Supplies119
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(Bor)124
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Low-Power Modes126
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Run Mode131
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Low-Power Modes132
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Sleep Mode133
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Stop 0 Mode135
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Stop 1 Mode138
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Standby Mode139
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Shutdown Mode141
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PWR Registers143
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PWR Register Map158
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Reset160
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Power Reset160
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System Reset160
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RTC Domain Reset162
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Clocks163
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HSE Clock167
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HSI16 Clock168
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HSI48 Clock169
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Pll169
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LSE Clock170
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LSI Clock170
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ADC Clock172
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RTC Clock172
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Timer Clock173
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Watchdog Clock173
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Low-Power Modes177
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RCC Registers178
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(Rcc_Apbsmenr1)205
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(Rcc_Apbsmenr2)208
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(Rcc_Ccipr2)212
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RCC Register Map217
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Introduction221
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CRS Interrupts225
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CRS Registers226
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CRS Register Map231
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Introduction232
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GPIO Registers241
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(X =A to F)241
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(X = a to F)242
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(X = a to F)243
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(X = a to F)244
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(X = a to F)245
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(X = a to F)246
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SYSCFG Registers248
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Introduction270
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From ADC to TIM1272
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And EXTI, to DAC273
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TIM16, and TIM17273
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And LPTIM2274
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And COMP3274
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TIM16, and TIM17275
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And TIM17275
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Introduction277
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Dma278
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DMA Transfers279
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DMA Arbitration280
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DMA Channels281
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DMA Interrupts286
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DMA Registers286
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DMA Register Map295
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Introduction298
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DMAMUX Mapping299
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DMAMUX Signals303
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DMAMUX Channels303
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DMAMUX Registers308
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(Dmamux_Cxcr)308
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(Dmamux_Csr)309
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(Dmamux_Cfr)309
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Main Features314
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EXTI Mux321
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EXTI Registers324
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Introduction336
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CRC Operation337
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CRC Registers339
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CRC Register Map342
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Introduction343
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ADC Connectivity352
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Timings357
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Data Management363
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Oversampler373
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Analog Watchdog375
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Triggered Mode375
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ADC Interrupts379
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ADC Registers381
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ADC Register Map402
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Introduction404
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DAC Data Format408
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DAC Conversion410
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DMA Requests411
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Noise Generation411
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Available)418
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DAC Interrupts423
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DAC Registers424
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(Dac_Dhr12L1)428
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(Dac_Dhr12L2)430
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(Dac_Dhr12Ld)431
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(Dac_Dhr8Rd)432
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(Dac_Shsr1)437
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(Dac_Shsr2)437
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DAC Register Map440
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Introduction442
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Introduction445
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Hysteresis449
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COMP Interrupts451
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COMP Registers451
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Introduction459
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RNG Operation464
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RNG Clocking465
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Error Management465
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RNG Interrupts467
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Introduction467
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Data Collection468
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RNG Registers469
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RNG Register Map472
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Introduction473
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AES Interrupts509
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AES Registers511
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AES Register Map521
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Time-Base Unit526
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Counter Modes528
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Clock Selection542
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PWM Input Mode549
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PWM Mode552
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One-Pulse Mode570
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DMA Burst Mode582
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Debug Mode583
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TIM1 Registers584
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(Tim1_Ccmr1)595
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(Tim1_Ccmr1)596
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(Tim1_Ccmr2)599
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(Tim1_Ccmr2)600
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(Tim1_Ccer)602
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(Tim1_Bdtr)608
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(Tim1_Dmar)613
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(Tim1_Ccmr3)614
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Time-Base Unit627
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Counter Modes629
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Clock Selection639
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PWM Input Mode646
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PWM Mode648
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One-Pulse Mode655
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DMA Burst Mode668
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Debug Mode669
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Time-Base Unit703
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Counting Mode705
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Clock Source708
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Debug Mode709
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Time-Base Unit717
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Counter Modes719
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Clock Selection722
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PWM Mode727
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One-Pulse Mode728
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Debug Mode729
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TIM14 Registers730
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Time-Base Unit745
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Counter Modes747
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Clock Selection752
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PWM Mode760
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One-Pulse Mode771
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DMA Burst Mode778
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Debug Mode780
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TIM15 Registers781
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(Tim15_Ccmr1)789
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(Tim15_Ccmr1)790
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Introduction831
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Glitch Filter835
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Prescaler836
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Operating Mode837
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Timeout Function839
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Register Update840
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Counter Mode841
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Timer Enable841
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Encoder Mode842
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Debug Mode844
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LPTIM Interrupts845
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LPTIM Registers845
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Introduction858
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Window Option859
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Debug Mode860
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IWDG Registers861
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Introduction867
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Debug Mode870
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WWDG Interrupts870
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WWDG Registers870
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Introduction873
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RTC Interrupts890
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RTC Registers890
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RTC Register Map910
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Introduction912
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Tamper Detection915
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TAMP Interrupts917
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TAMP Registers917
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Introduction927
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Mode Selection931
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Software Reset937
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Data Transfer938
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I2C Slave Mode940
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I2C Master Mode949
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Smbus Slave Mode968
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Error Conditions976
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DMA Requests978
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Debug Mode979
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I2C Interrupts980
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I2C Registers981
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I2C Register Map996
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USART Implementation1000
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USART Block Diagram1002
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USART Signals1003
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USART Transmitter1006
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USART Receiver1010
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USART Parity Control1025
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USART Smartcard Mode1033
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USART Interrupts1049
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USART Registers1050
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USART Register Map1084
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Transmitter (LPUART)1086
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LPUART Introduction1086
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LPUART Main Features1087
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LPUART Block Diagram1089
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LPUART Signals1090
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LPUART Transmitter1092
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LPUART Receiver1095
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LPUART Interrupts1113
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LPUART Registers1114
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LPUART Register Map1137
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Introduction1139
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SPI Main Features1139
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I2S Main Features1140
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General Description1141
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Configuration of SPI1149
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SPI Status Flags1160
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SPI Error Flags1161
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NSS Pulse Mode1162
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TI Mode1162
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CRC Calculation1163
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SPI Interrupts1165
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Figure 376. I1169
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Start-Up Description1174
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Clock Generator1176
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Figure 391. I1176
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I 2 S Master Mode1179
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I 2 S Slave Mode1180
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I2S Status Flags1182
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I2S Error Flags1183
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DMA Features1184
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I2S Interrupts1184
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SPI/I2S Register Map1195
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Introduction1196
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FDCAN Main Features1198
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Bit Timing1200
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Operating Modes1201
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Message RAM1211
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FDCAN Registers1227
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(Fdcan_Txbtie)1255
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(Fdcan_ Txbcie)1255
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FDCAN Register Map1258
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Introduction1262
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USB Main Features1262
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USB Implementation1262
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Common Registers1283
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USB Register Map1306
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Introduction1308
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UCPD Main Features1308
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UCPD Implementation1308
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UCPD Block Diagram1310
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Table 236. Data Size1315
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UCPD BMC Transmitter1319
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UCPD BMC Receiver1320
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UCPD DMA Interface1322
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UCPD Low-Power Modes1327
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UCPD Interrupts1328
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UCPD Registers1329
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(Ucpd_Rx_Ordextr1)1344
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(Ucpd_Rx_Ordextr2)1344
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UCPD Register Map1345
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Introduction1347
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HDMI-CEC Pin1348
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Message Description1348
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Table 242. HDMI Pin1348
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Bit Timing1349
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Figure 416. Blocks1349
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Arbitration1350
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SFT Option Bit1351
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Error Handling1352
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Bit Error1352
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Message Error1352
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HDMI-CEC Interrupts1356
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HDMI-CEC Registers1357
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Debug Support (DBG)1365
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Overview1365
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SWD Port Pins1366
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SW-DP Pin Assignment1366
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SWD Port1367
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SW-DP Registers1369
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SW-AP Registers1370
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Core Debug1371
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BPU Functionality1372
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DWT Functionality1372
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DBG Registers1373
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DBG Register Map1377
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Revision History1382
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