ST STM32G4 Series Reference Manual page 1387

RM0440
29.8.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17)
Address offset: 0x2C
Reset value: 0x0000 FFFF
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:0 ARR[19:0]: Auto-reload value
29.8.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17)
Address offset: 0x30
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 REP[7:0]: Repetition counter reload value
•
•
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 29.4.3: Time-base unit on page 1305
update and behavior.
The counter is blocked while the auto-reload value is null.
Non-dithering mode (DITHEN = 0)
The register holds the auto-reload value in ARR[15:0]. The ARR[19:16] bits are reset.
Dithering mode (DITHEN = 1)
The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered
part.
12 11 10 9
Res. Res. Res.
This bitfield defines the update rate of the compare registers (i.e. periodic transfers from
preload to active registers) when preload registers are enable. It also defines the update
interrupt generation rate, if this interrupt is enable.
When the repetition down-counter reaches zero, an update event is generated and it
restarts counting from REP value. As the repetition counter is reloaded with REP value only
at the repetition update event UEV, any write to the TIMx_RCR register is not taken in
account until the next repetition update event.
It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-
aligned mode:
the number of PWM periods in edge-aligned mode
the number of half PWM period in center-aligned mode
General-purpose timers (TIM15/TIM16/TIM17)
24 23 22
Res. Res. Res.
8 7 6
ARR[15:0]
rw rw rw
8 7 6
Res.
rw rw
RM0440 Rev 1
21 20 19 18
Res. Res. ARR[19:16]
rw rw
5 4 3 2
rw rw rw rw
for more details about ARR
5 4 3 2
REP[7:0]
rw rw rw rw
17 16
rw rw
1 0
rw rw
1 0
rw rw
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