ST STM32G4 Series Reference Manual page 1347

RM0440
Bit 7 TI1S: tim_ti1 selection
0: The tim_ti1_in[15..0] multiplexer output is connected to tim_ti1 input
1: The tim_ti1_in[15..0] and tim_ti2_in[15..0] multiplexers output are connected to the tim_ti1
input (XOR combination)
Bits 6:4 MMS[2:0]: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (tim_trgo). The combination is as follows:
000: Reset - the UG bit from the TIM15_EGR register is used as trigger output (tim_trgo). If
001: Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is
010: Update - The update event is selected as trigger output (tim_trgo). For instance a
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to
100: Compare - tim_oc1ref signal is used as trigger output (tim_trgo).
101: Compare - tim_oc2ref signal is used as trigger output (tim_trgo).
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bit 2 CCUS: Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, must be kept at reset value.
Bit 0 CCPC: Capture/compare preloaded control
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
Note: This bit acts only on channels that have a complementary output.
the reset is generated by the trigger input (slave mode controller configured in reset
mode) then the signal on tim_trgo is delayed compared to the actual reset.
useful to start several timers at the same time or to control a window in which a slave
timer is enable. The Counter Enable signal is generated by a logic AND between CEN
control bit and the trigger input when configured in gated mode. When the Counter
Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if
the master/slave mode is selected (see the MSM bit description in TIM15_SMCR
register).
master timer can then be used as a prescaler for a slave timer.
be set (even if it was already high), as soon as a capture or a compare match
occurred (tim_trgo).
the COMG bit only.
the COMG bit or when an rising edge occurs on tim_trgi.
only when a commutation event (COM) occurs (COMG bit set or rising edge detected on
tim_trgi, depending on the CCUS bit).
General-purpose timers (TIM15/TIM16/TIM17)
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