Timer Status Registers 1 And 2; Table 12-7 Timer Status Register Description - Motorola MC68VZ328 User Manual

Programming Model
12.2.6

Timer Status Registers 1 and 2

Each timer status (TSTATx) register indicates the corresponding timer's status. When a capture event
occurs, it is indicated by setting the CAPT bit. When a compare event occurs, the COMP bit is set. Both
bits are cleared by writing 0x0. To be cleared, these bits must first be examined, and the bit must have a
value of 0x1. This ensures that an interrupt will not be missed if it occurs between the status read and when
the interrupt is cleared. The settings for the registers are described in Table 12-7.
TSTAT1
BIT
14
15
TYPE rw rw
0 0
RESET
TSTAT2
BIT
14
15
TYPE rw rw
0 0
RESET
Name
Not used These bits are not used.
Bits 15–2
CAPT Capture Event—This status bit, when set,
Bit 1 indicates that a capture event occurred.
COMP Compare Event—This status bit, when set,
Bit 0 indicates when a compare event occurs.
12-12
Timer Status Register 1
13 12 11 10
Not Used
rw rw rw rw
0 0 0 0
Timer Status Register 2
13 12 11 10
Not Used
rw rw rw rw
0 0 0 0
Table 12-7. Timer Status Register Description
Description
MC68VZ328 User's Manual
9 8 7 6 5
rw rw rw rw rw
0 0 0 0 0
0x0000
9 8 7 6 5
rw rw rw rw rw
0 0 0 0 0
0x0000
0 = No capture event occurred.
1 = A capture event has occurred.
0 = No compare event occurred.
1 = A compare event has occurred.
0x(FF)FFF60A
4 3 2 1
CAPT COMP
rw rw rw rw
0 0 0 0
0x(FF)FFF61A
4 3 2 1
CAPT COMP
rw rw rw rw
0 0 0 0
Setting
—
BIT 0
rw
0
BIT 0
rw
0