Timer Reference Registers (Trr0–Trr3) - Motorola DigitalDNA ColdFire MCF5272 User Manual

General-Purpose Timer Registers
Bits Name
15–8 PS Prescaler. Programmed to divide the clock input by values from 1 to 256. The value 0000_0000
divides the clock by 1; the value 1111_1111 divides the clock by 256.
7–6 CE Capture edge and enable interrupt.
00 Disable capture and interrupt on capture event
01 Capture on rising edge only and generate interrupt on capture event
10 Capture on falling edge only and generate interrupt on capture event
11 Capture on any edge and generate interrupt on capture event
5 OM Output mode (TMR0 and TMR1 only. Reserved in TMR2 and TMR3)
0 Active-low pulse for one system clock cycle (15 nS at 66 MHz)
1 Toggle output
TOUTn is high at reset but is unavailable externally until the appropriate port control register is
configured for this function. See Section 17.2, "Port Control Registers."
4 ORI Output reference interrupt enable
0 Disable interrupt for reference reached (does not affect interrupt on capture function)
1 Enable interrupt upon reaching the reference value If ORI is 1 when the TER[REF] is set, an
immediate interrupt occurs.
3 FRR Free run/restart
0 Free run. Timer count continues to increment after the reference value is reached.
1 Restart. Timer count is reset immediately after the reference value is reached.
2–1 CLK Input clock source for the timer
00 Stop count
01 Master system clock
10 Master system clock divided by 16. TIN0 and TIN1 are external to the MCF5272 and are not
synchronized to the system clock, so successive timeout lengths may vary slightly.
11 Corresponding TIN pin, TIN0 or TIN1 (falling edge), unused in TMR2 and TMR3
The minimum high and low periods for TIN as the clock source is 1 system clock, which gives a
maximum TIN frequency of clock/2.
0 RST Reset timer.
0 A transition from 1 to 0 resets the timer. Other register values can be written. The
counter/timer/prescaler are not clocked unless the timer is enabled.
1 Enable timer
15.3.2 Timer Reference Registers (TRR0–TRR3)
Each TRR holds a 16-bit reference value that is compared with the free-running TCN as
part of the output compare function. A match occurs when TCN increments to equal TRR.
15
Field
Reset
R/W
Addr
Figure 15-3. Timer Reference Registers (TRR0–TRR3)
15-4
Table 15-1. TMRn Field Descriptions
REF (16-bit reference value)
1111_1111_1111_1111
MBAR + 0x204 (TRR0); 0x224 (TRR1); 0x244 (TRR2); 0x264 (TRR3)
MCF5272 User's Manual
Description
Read/Write
0