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HARDWARE PREPARATION
2.3.6
DRAM
Address Multiplex Select (J8)
The MVME135/136 design requires high performance memory devices.
These devices have timing requirements that differ from typical
performance DRAMs. Jumper block J8 allows the flexibility to accept
t i mi ng
from a wider vari ety of DRAM devi ces
and
is
factory
configured.
Jumper Block J8
Normal High Performance
DRAM Multiplex Timing
(Factory Setting)
2
3
+--
1
o
2.3.7 Loca1/VMEbus Timeout Disable
(Jll)
Jumper block Jll performs a hardware enable/disable of the local and
VMEbus timeout. This jumper is typically used when debugging a new
design or isolating a problem where bus errors occur due to accesses
to non-existent memory space. Install ing a jumper cap across jumper
Jll pins 1 and
2
will prevent the cycle from being terminated by a bus
error when a slave does not respond. This allows ease in debug since
the hung access will remain as long as the cyc1 e is not termi nated by
a normal acknowl edge.
When 135bug is installed, the MVME135/136 will not come up
if
a
jumper cap is installed at Jll pins 1 and 2. This is due to the fact
that as a course of normal operation, 135bug initiates bus cycles
that may be terminated by a timeout. These cycles include searching
for on-board coprocessors (FPCP or PMMU) or sizing of system memory.
If the MVME135/136 is set as the system controller, then VMEbus
timeout is not affected by jumper Jll, and Jll only controls the
local bus timeout. The MVME135/136 will not cause a VMEbus timeout
if
not set as the system controller, that function is provided to the
module that has been configured as VMEbus system controller.
2-8
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