Sram Base Address Register (Rambar) - Motorola DigitalDNA ColdFire MCF5272 User Manual

4.3.2.1 SRAM Base Address Register (RAMBAR)

RAMBAR determines the base address location of the internal SRAM module, as well as
the definition of the types of accesses allowed for it.
• RAMBAR is a 32-bit write-only supervisor control register. It is accessed in the
CPU address space via the MOVEC instruction with an Rc encoding of 0xC04.
RAMBAR can be read or written in background debug mode (BDM). At system
reset, the V bit is cleared and the remaining bits are uninitialized. To access the
SRAM module, RAMBAR must be written with the appropriate base address after
system reset.
• The SRAM base address register (RAMBAR) can be accessed only in supervisor
mode using the MOVEC instruction with an Rc value of 0xC04.
31
Field
Reset
R/W
Address
Figure 4-1. SRAM Base Address Register (RAMBAR)
RAMBAR fields are described in Table 4-2.
Bits Name
31–12 BA Base address. SRAM module base address. The SRAM module occupies a 4-Kbyte space
defined by BA. SRAM can reside on any 4-Kbyte boundary in the 4-Gbyte address space.
11–9 — Reserved, should be cleared.
8 WP Write protect. Controls read/write properties of the SRAM.
0 Allows read and write accesses to the SRAM module.
1 Allows only read accesses to the SRAM module. Any attempted write reference generates an
access error exception to the ColdFire processor core.
7–6 — Reserved, should be cleared.
BA
W for CPU; R/W for debug
CPU space + 0xC04
Table 4-2. RAMBAR Field Description
Chapter 4. Local Memory
12 11 9 8 7 6
— WP —
—
Description
SRAM Overview
5 4 3 2 1 0
C/I SC SD UC UD V
0
4-3