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The PMC registers can be accessed with mtspr and mfspr using following SPR numbers:
•
PMC1 is SPR 953
•
PMC2 is SPR 954
•
PMC3 is SPR 957
•
PMC4 is SPR 958
2.1.2.4.6 User Performance Monitor Counter Registers (UPMC1-UPMC4)
The contents of the PMC1-PMC4 are reflected to UPMC1-UPMC4, which can be read by
user-level software. The UPMC registers can be read with mfspr using the following SPR
numbers:
•
UPMC1 is SPR 937
•
UPMC2 is SPR 938
•
UPMC3 is SPR 941
•
UPMC4 is SPR 942
2.1.2.4.7 Sampled Instruction Address Register (SIA)
The sampled instruction address register (SIA) is a supervisor-level register that contains
the effective address of an instruction executing at or around the time that the processor
signals the performance monitor interrupt condition. The SIA is shown in Figure 2-8.
Instruction Address
31
Figure 2-8. Sampled instruction Address Registers (SIA)
If the performance monitor interrupt is triggered by a threshold event, the SIA contains the
exact instruction (called the sampled instruction) that caused the counter to overflow.
If the performance monitor interrupt was caused by something besides a threshold event,
the SIA contains the address of the last instruction completed during that cycle. SIA can be
accessed with the mtspr and mfspr instructions using SPR 955.
2.1.2.4.8 User Sampled Instruction Address Register (USIA)
The contents of SIA are reflected to USIA, which can be read by user-level software. USIA
can be accessed with the mfspr instructions using SPR 939.
2.1.2.4.9 Sampled Data Address Register (SDA) and User Sampled Data
Address Register (USDA)
The MPC750 does not implement the sampled data address register (SDA) or the
user-level, read-only USDA registers. However, for compatibility with processors that do,
those registers can be written to by boot code without causing an exception. SDA is
SPR 959; USDA is SPR 943.
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MPC750 RISC Microprocessor User's Manual
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