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The CPU12 uses all M68HC11 modes as well as new forms of indexed addressing.
Differences between M68HC11 and M68HC12 indexed modes are described in
dexed Addressing
in
3.9 Instructions Using Multiple
3.2 Effective Address
Each addressing mode except inherent mode generates a 16-bit effective address
which is used during the memory reference portion of the instruction. Effective address
computations do not require extra execution cycles.
3.3 Inherent Addressing Mode
Instructions that use this addressing mode either have no operands or all operands
are in internal CPU registers. In either case, the CPU does not need to access any
memory locations to complete the instruction.
Examples:
NOP
INX
3.4 Immediate Addressing Mode
Operands for immediate mode instructions are included in the instruction stream, and
are fetched into the instruction queue one 16-bit word at a time during normal program
fetch cycles. Since program data is read into the instruction queue several cycles be-
fore it is needed, when an immediate addressing mode operand is called for by an in-
struction, it is already present in the instruction queue.
The pound symbol (#) is used to indicate an immediate addressing mode operand.
One very common programming error is to accidentally omit the # symbol. This causes
the assembler to misinterpret the following expression as an address rather than ex-
plicitly provided data. For example LDAA #$55 means to load the immediate value $55
into the A accumulator, while LDAA $55 means to load the value from address $0055
into the A accumulator. Without the # symbol the instruction is erroneously interpreted
as a direct addressing mode instruction.
Examples:
LDAA
LDX
LDY
These are common examples of 8-bit and 16-bit immediate addressing mode. The
size of the immediate operand is implied by the instruction context. In the third exam-
ple, the instruction implies a 16-bit immediate value but only an 8-bit value is supplied.
In this case the assembler will generate the 16-bit value $0067 because the CPU ex-
pects a 16-bit value in the instruction stream.
BRSET
MOTOROLA
3-2
Modes. Instructions that use more than one mode are discussed
Modes.
;this instruction has no operands
;operand is a CPU register
#$55
#$1234
#$67
FOO,#$03,THERE
ADDRESSING MODES
3.8 In-
CPU12
REFERENCE MANUAL
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