Sdram Address Multiplexing - Motorola MPC8240 User Manual

SDRAM Interface Operation
Table 6-5. Supported SDRAM Device Configurations
SDRAM
Device
Device
Organization
Density
4M x 4 bits
16 Mbit
(2 banks)
2M x 8 (or 9) bits
1M x 16 (or 18) bits
16M x 4 bits
64 Mbit
8M x 8 (or 9) bits
(2 banks)
4M x 16 (or 18) bits
16M x 4 bits
8M x 8 (or 9) bits
64 Mbit
(4 banks)
4M x 16 (or 18) bits
2M x 32 (or 36) bits
16M x 8 (or 9) bits
128 Mbit
8M x 16 (or 18) bits
(2 Banks)
4M x 32 (or 36) bits
16M x 8 (or 9) bits
128 Mbit
8M x 16 (or 18) bits
(4 Banks)
4M x 32 (or 36) bits
16M x 16 (or 18) bits
256 Mbit
(4 banks)
1
A logical bank is defined for the MPC8240 as a portion of memory addressed through an SDRAM bank select.
2
A physical bank is defined for the MPC8240 as a portion of memory addressed through an SDRAM chip select.
Certain modules of SDRAM may have two physical banks and require two chip selects to be programmed to
support a single module.
3
Number of devices and size for physical banks are based on a 64-bit data bus, for a 32-bit data bus these
values would be halved.
4
The physical bank size is the amount of memory addressed by a single SDRAM chip select.
5
Not supported for 32-bit data bus

6.2.2 SDRAM Address Multiplexing

This section describes how the MPC8240 translates processor addresses into SDRAM
memory addresses.
The MPC8240 SDRAM memory address signals SDMA[12:0] are labeled with SDMA12
as the most-significant bit (msb) and SDMA0 as the least-significant bit (lsb). Most
SDRAM devices are labeled with A0 as the least significant address input. Therefore, the
MPC8240 SDMA[12:0] signals should be connected to SDRAM devices according to
Table 6-2.
Table 6-6 shows the multiplexing of the internal physical addresses A[0
SDBA[1:0] and SDMA[12:0] during the row and column phases when operating in 32-bit
mode.
6-10
Addressing—Row
Bits x Column
Bits x Logical
1
Banks
5
13 x 8 x 2
11 x 10 x 2
11 x 9 x 2
5
11 x 8 x 2
13 x 10 x 2
13 x 9 x 2
5
13 x 8 x 2
12 x 10 x 4
12 x 9 x 4
5
12 x 8 x 4
5
11 x 8 x 4
13 x 10 x 2
13 x 9 x 2
5
13 x 8 x 2
12 x 10 x 4
12 x 9 x 4
5
12 x 8 x 4
12 x 10 x 4
MPC8240 Integrated Processor User's Manual
MCCR1 Number of
[Bank n row] Devices in a
setting Physical Bank
0b01 16
0b11
0b11 8
0b11 4
0b01 16
0b01 8
0b01 4
0b00 16
0b00 8
0b00 4
0b00 2
0b01 8
0b01 4
0b01 2
0b00 8
0b00 4
0b00 2
0b00 4
Physical
3,4
Bank Size
2 , 3
(Mbytes)
32
16
8
128
64
32
128
64
32
16
128
64
32
128
64
32
128
:31 ] through
msb lsb