Frc Offset Control; Cursor And Blinking Rate Control; Low-Power Mode - Motorola DragonBall MC68328 User Manual

LCD Controller

4.5.6 FRC Offset Control

4.5.7 Cursor and Blinking Rate Control

4.5.8 Low-Power Mode

Some panels may have a signal called PANEL_OFF that turns off the panel for low-power
mode. In the MC68328 processor system, this signal is not supported. Instead, use a paral-
lel I/O pin to perform this function.
The software sequence to achieve PANEL_OFF using parallel I/O consists of 2 steps:
1. Turn off the VLCD (+15V or -15V) by I/O driving a transistor
2. Turn off the LCDON bit
To exit from LCDC-off mode:
1. Turn on the LCDON bit
2. Delay for 1-2ms
3. Turn on the VLCD by I/O driving a transistor
When setting the LCDON bit (register CKCON bit 7) to 1, LCDC itself will enter a low-power
mode by stopping its own pixel clock prior to the next line-buffer-fill DMA. Additional screen
DMA and display-refresh operations will then be stopped in this mode. When the LCDC is
switched back on, DMA and screen-refresh activities will resume in a synchronous fashion.
Software should check that the actual PANEL_OFF signal is de-asserted before setting
LCDON to a 1.
4-10 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
Table 4-2. Gray Scale Code Mapping
Code Mapping
Data
00
01
10
11
Table 4-3. Gray Palette Selection
Gray Palette
Gray Code
000
001
010
011
100
101
110
111
Gray code
G02G01G00
G12G11G10
G22G21G20
G32G31G30
Density
0
1/4
5/16
1/2
11/16
3/4
1
1
MOTOROLA