Page-Hit Cpu Read Cycle In Power-Down Mode (Cas Latency = 1, Bit Apen Of Sdram Power-Down Register = 1); Figure 19-21 Page-Hit Cpu Read Cycle In Power-Down Mode Timing Diagram - Motorola MC68VZ328 User Manual

19.3.20 Page-Hit CPU Read Cycle in Power-down Mode (CAS
Latency = 1, Bit APEN of SDRAM Power-down
Register = 1)
Figure 19-21 shows the timing diagram for the page-hit CPU read cycle in power-down mode. The signal
values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information
about the operation of individual signals can be found in both Chapter 8, "LCD Controller," and Chapter 7,
"DRAM Controller."
S0
SDCLK
SCKEN
A[16:1]/MD[15:0]
SDA10
CS
RAS
CAS
D[15:0]
WE
DQM
DTACK
Figure 19-21. Page-Hit CPU Read Cycle in Power-down Mode Timing Diagram
S1 S2 S3 S4 S4 S4
7
Electrical Characteristics
S4 S4 S4 S4 S5 S6
Col
Read
Command
AC Electrical Characteristics
S7
19-25