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If there are no prior instructions waiting in the address queue, the load/store instruction is
issued to the data cache immediately at the time the instruction is taken. Otherwise, if there
are prior instructions remaining whose addresses have not yet been issued to the data
cache, the instruction is inserted into the address queue and data is inserted into the
respective store data queue. For load/store with update instructions, the destination address
register is written back on the following clock, regardless of the address queue's state.
6.6.2 Serializing Load/Store Instructions
The following load/store instructions are not taken until all previous instructions have
terminated.
• Load/store multiple instructions—lmw, stmw
• Storage synchronization instructions—lwarx, stwcx, sync
• String instructions—lswi, lswx, stswi, stswx
• Move to internal special registers and move to off-core special registers
The following load/store instructions must terminate before more instructions can be issued.
• Load/store multiple instructions—lmw, stmw
• Storage synchronization instructions—lwarx, stwcx, sync
• String instructions—lswi, lswx, stswi, stswx
6.6.3 Instructions Issued to the Data Cache
The load/store unit pipelines load accesses. The individual cache cycles of all multiregister
instructions and unaligned accesses are pipelined into the data cache interface.
6.6.4 Issuing Store Instruction Cycles
A new store instruction is not issued to the data cache until all prior instructions have
terminated without an exception because the core supports the precise interrupt model. If a
load instruction is followed by a store instruction, a one clock delay is inserted between the
load bus cycle termination and the store cycle issue.
6.6.5 Issuing Nonspeculative Load Instructions
Load instructions targeted at a nonspeculative memory region are identified as
nonspeculative one clock cycle after the previous load/store bus cycle termination, but only
if all prior instructions have terminated normally and without an exception. The
nonspeculative identification relates to the state of the cycle's associated instruction. For
lmw, although the cycles are pipelined into the bus, they are all marked as nonspeculative
because the instruction is nonspeculative.
With a single register load instruction where more than one bus cycle is generated, some of
the cycles can be marked as speculative and later cycles can be marked as nonspeculative
after all prior instructions terminate. When executing speculative load cycles to the
nonspeculative external memory region, no external cycles are generated until the load
instruction becomes nonspeculative.
MOTOROLA
MPC823e REFERENCE MANUAL
The PowerPC Core
6-27
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