Buffer Accesses (Fifo Mode) - Motorola DigitalDNA MPC180E User Manual

EBI Controller Operation
Table 3-8 summarizes the operation in clock cycles of the EBI in MPC860 and MPC8260
modes.
Single beat read/write to/from EBI register or FIFO
Single beat read/write to/from execution units
4-beat burst read/write to/from FIFOs
4-beat burst read/write to/from execution units
8-beat burst read/write to/from FIFOs
8-beat burst read/write to/from execution units
Single accesses are those that are only to one address and for which one 32-bit data word
is transferred. For writes or reads to the execution units, it is possible that the EBI will
generate one or more wait states to the host. This is a function of the current programming
of the EBI registers and the state of the execution unit being addressed. At no time will the
EBI generate a wait state for an access to an EBI register (CSTAT, ID, IMASK, IBCTL,
IBCNT, OBCTL, OBCNT).
Burst accesses are defined as exactly four (MPC860 mode) or eight (MPC8260 mode)
32-bit writes or reads at consecutive addresses. A burst transfer begins by the assertion of
CS, TS, and BURST along with the address.

3.4.1 Buffer Accesses (FIFO Mode)

The controller contains an input buffer and an output buffer of 4096 bits each. These buffers
can be written to directly by the host or by using DMA. For direct access, the host simply
writes or reads the address of the buffer.
DREQ1 and DREQ2 (input/output buffer ready) are programmable handshake signals used
for buffer control. An external DMA controller can use this handshake to service the input
or output buffer with data transfers as required. The EBI CSTAT register determines
whether these signals reflect the state of the input buffer or output buffer. By default,
DREQ1 refers to the state of the input buffer and DREQ2 refers to the state of the output
buffer.
DREQx refers to either DREQ1 or DREQ2. Either can be
programmed to refer to the state of the input or output buffer.
In FIFO mode, the input buffer automatically fills and the output buffer automatically
empties. In the input buffer, this is accomplished by assertion of DREQx whenever at least
four 32-bit words (in MPC860 mode) or eight 32-bit words (in MPC8260 mode) of space
are available. Similarly, for the output buffer, DREQx remains asserted as long as at least
four 32-bit words (MPC860 mode) or eight 32-bit words (MPC8260 mode) are in the
output buffer to be read.
3-12
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 3-8. EBI Operation Summary
Name
NOTE:
MPC180E Security Processor User's Manual
MPC860 Mode MPC260 Mode
CONFIG=0 CONFIG=1
0 2
at least 2 at least 3
0 not supported
not supported not supported
not supported 2
not supported not supported