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Programming Model
6.2.8.3 Watchdog Counter Register (WCR)
The WCR, Figure 6-10, contains the 16 most significant bits of the software watchdog
counter. Writing any value to WCR resets the counter and prescaler and should be executed
on a regular basis if the watchdog is enabled.
15
Field
Reset
R/W
Address
Figure 6-10. Watchdog Counter Register (WCR)
6.2.8.4 Watchdog Event Register (WER)
The WER, Figure 6-11, reports when the watchdog timer reaches the WIRR value.
15
Field
Reset
R/W
Address
Table 6-11 describes WER fields.
Bits
Field
15–1
—
Reserved, should be cleared.
0
WIE
Watchdog interrupt event.
0 WIRR value has not been reached.
1 WIRR value has been reached.
WIE is cleared by writing a 1 to it. The timer does not negate the interrupt request to the interrupt
controller until WIE is cleared. WIE is set regardless of the state of WIRR[IEN]; however, an interrupt is
not asserted to the controller unless WIRR[IEN] = 1.
6-14
0000_0000_0000_0000
0000_0000_0000_0000
Figure 6-11. Watchdog Event Register (WER)
Table 6-11. WER Field Descriptions
MCF5272 User's Manual
COUNT
R/W
MBAR + 0x288
—
R/W
MBAR + 0x28C
Description
0
1
0
WIE
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