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2.3.1.2 Address Registers
Each address register and stack pointer holds a 32-bit address.
Address
. registers cannot be used for byte-sized operands. When an address register is
used as a source operand, either the low-order word or the entire long-word
operand is used, depending upon the operation size.
When an address
register is used as a destination operand, the entire register is affected,
regardless of operation size. If the source operand is a word, it is first sign
extended to 32 bits, and then used in the operation. Address registers can be
used to support address computation. The instruction set includes instructions
that add to, subtract from, compare, and move the contents of address registers.
Figure 2-5 shows the organization of addresses in address registers.
31
16 15
o
SIGN EXTENDED
16-BIT ADDRESS OPERAND
31
o
FULL 32-BIT ADDRESS OPERAND
Figure 2-5. Address Organization in Address Registers
2.3.1.3 Control Registers
The control registers contain control information for supervisor functions. The
registers vary in size. With the exception of the user portion of the SR (CCR),
they are accessed only by instructions at the supervisor privilege level.
The SR shown in Figure 2-3 is 16 bits wide. Only 11 bits of the SR are defined,
and all undefined values are reserved by Motorola for future definition. The
undefined bits are read as zeros and should be written as zeros for future
compatibility. The lower byte of the SR is the CCR. Operations to the CCR can
be performed at the supervisor or user privilege level. All operations to the SR
and CCR are word-size operations. For all CCR operations, the upper byte is
read as all zeros and is ignored when written, regardless of privilege level.
The alternate function code registers (SFC and DFC) are 32-bit registers with
only bits [2:0] implemented. These bits contain address space values (FC2 to
FCO) for the read or write operand of the MOVES instruction. The MOVEC
instruction is used to transfer values to and from the alternate function code
registers. These are long-word transfers - the upper 29 bits are read as zeros
and are ignored when written.
MOTOROLA
2-6
ARCHITECTURE SUMMARY
CPU32 REFERENCE MANUAL
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