Granularity Examples; Spi Word Length Wl - Texas Instruments CC3235 SimpleLink Series Technical Reference Manual

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Table 8-4 lists granularity examples with a clock source frequency of 48 MHz.
MCSPI_CHC
ONF F
ratio
[CLKD]
0 1
1 2
2 4
3 8
8.2.3.4.1 FIFO Buffer Management
The SPI controller has a built-in 64-byte buffer to unload the DMA or interrupt handler and improve data
throughput. This buffer can be used by setting MCSPI_CHCONF[FFER]
MCSPI_CHCONF[FFEW]
• Master or slave mode
• Every word length MCSPI_CHCONF[WL] are supported.
Two levels, AEL and AFL, in the MCSPI_XFERLEVEL register, rule the buffer management. The driver
must set these values as a multiple of SPI word length defined in MCSPI_CHCONF[WL]. The number of
bytes written in the FIFO depends on word length (see
when the channel is enabled, or when the FIFO configuration changes.
Number of bytes written
in the FIFO
8.2.3.4.1.1 Split FIFO
The FIFO can be split into two parts when the module is configured in transmit/receive mode,
MCSPI_CHCONF[TRM] set to 0, and MCSPI_CHCONF[FFER]
MCSPI_CHCONF[FFEW]
byte-deep FIFO per direction. See
SWRU543 – January 2019
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Table 8-4. Granularity Examples
MCSPI_CHC MCSPI_CHC
ONF ONF
[PHA] [POL]
X X
X X
X X
X X
[FFWE]? See figs. 6 to 9.
Table 8-5. SPI Word Length WL
8
2 bytes
[FFWE]? See figs. 6 to 9.
Figure 8-7,
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T T
high low
(ns) (ns)
10.4 10.4
20.8 20.8
41.6 41.6
83.2 83.2
to 1. The buffer can be used in the following modes:
Table 8-5). The FIFO buffer pointers are reset
SPI Word Length
[FFRE]? See figs. 6 to
are asserted. Then the system can access a 32-
Figure 8-8, Figure 8-9, and
Functional Description
T
period
Duty Cycle
(ns)
20.8 50-50
41.6 50-50
83.2 50-50
166.4 50-50
[FFRE]? See figs. 6 to 9.
16 and 32
4 bytes
9.and
Figure 8-10.
SPI (Serial Peripheral Interface)
F
out
(MHz)
48
24
12
6
or
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