ST STM32G4 Series Reference Manual page 1453

RM0440
Data append
This section describes different ways of appending data for processing, where the size of
data to process is not a multiple of 128 bits.
For ECB or CBC mode, refer to
The last block management in these cases is more complex than in the sequence described
in this section.
Data append through polling
This method uses flag polling to control the data append through the following sequence:
1. Enable the AES peripheral by setting the EN bit of the AES_CR register.
2. Repeat the following sub-sequence until the payload is entirely processed:
a)
b)
c)
d)
3. Discard the data that is not part of the payload, then disable the AES peripheral by
clearing the EN bit of the AES_CR register.
Note: Up to three wait cycles are automatically inserted between two consecutive writes to the
AES_DINR register, to allow sending the key to the AES processor.
NPBLB bits are not used in header phase of GCM, GMAC and CCM chaining modes.
Data append using interrupt
The method uses interrupt from the AES peripheral to control the data append, through the
following sequence:
1. Enable interrupts from AES by setting the CCFIE bit of the AES_CR register.
2. Enable the AES peripheral by setting the EN bit of the AES_CR register.
3. Write first four input data words into the AES_DINR register.
4. Handle the data in the AES interrupt service routine, upon interrupt:
a)
b)
c)
Write four input data words into the AES_DINR register.
Wait until the status flag CCF is set in the AES_SR, then read the four data words
from the AES_DOUTR register.
Clear the CCF flag, by setting the CCFC bit of the AES_CR register.
If the data block just processed is the second-last block of the message and the
significant data in the last block to process is inferior to 128 bits, pad the
remainder of the last block with zeros and, in case of GCM payload encryption or
CCM payload decryption, specify the number of non-valid bytes, using the NPBLB
bitfield of the AES_CR register, for AES to compute a correct tag.
Read four output data words from the AES_DOUTR register.
Clear the CCF flag and thus the pending interrupt, by setting the CCFC bit of the
AES_CR register
If the data block just processed is the second-last block of an message and the
significant data in the last block to process is inferior to 128 bits, pad the
remainder of the last block with zeros and, in case of GCM payload encryption or
CCM payload decryption, specify the number of non-valid bytes, using the NPBLB
Section 33.4.6: AES ciphertext stealing and data
RM0440 Rev 1
AES hardware accelerator (AES)
padding.
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