Table 1-4. Raven Mpc Register Values For Chrp Memory Map - Motorola MVME3600 Series Programmer's Reference Manual

2. To enable the "Processor-hole" area, program the Falcon chipset to
3. Programmable via Raven ASIC.
4. CHRP requires the starting address for the PCI memory space to be
5. Programmable via Raven ASIC for either contiguous or spread-I/O
6. The actual size of each ROM/Flash bank may vary.
7. The first 1MB of ROM/Flash Bank A appears at this range after a
8. This range can be mapped to the VMEbus by programming the
9. The only method of generating a PCI Interrupt Acknowledge cycle
The following table shows the programmed values for the associated
Raven MPC registers for the processor CHRP memory map.

Table 1-4. Raven MPC Register Values for CHRP Memory Map

Address
FEFF 0040
FEFF 0044
FEFF 0048
FEFF 004C
FEFF 0050
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ignore 0x000A0000 - 0x000BFFFF address range and program the
Raven to map this address range to PCI memory space.
256MB-aligned.
mode.
reset if the rom_b_rv control bit in the Falcon chip is cleared and the
rom_a_rv control bit is set. If the rom_b_rv control bit is set then
this address range maps to ROM/Flash Bank B.
Universe ASIC accordingly. The map shown is the recommended
setting which uses the Special PCI Slave Image and two of the four
programmable PCI Slave Images.
(8259 IACK) is to perform a read access to the Raven's PIACK
register at 0xFEFF0030.
Register Name
MSADD0
MSOFF0 & MSATT0
MSADD1
MSOFF1 & MSATT1
MSADD2
Programming Model
Register Value
4000 FCFF
0000 00C2
FD00 FDFF
0300 00C2
0000 0000
1
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