Dram Hidden Refresh Cycle (Low-Power Mode); Figure 19-8 Dram Hidden Refresh Cycle (Normal Mode) Timing Diagram; Figure 19-9 Dram Hidden Refresh Cycle (Low-Power Mode) Timing Diagram; Table 19-10 Dram Hidden Refresh Cycle (Normal Mode) Timing Parameters - Motorola MC68VZ328 User Manual

AC Electrical Characteristics
CASx
RASx
DWE
Figure 19-8. DRAM Hidden Refresh Cycle (Normal Mode) Timing Diagram
Table 19-10. DRAM Hidden Refresh Cycle (Normal Mode) Timing Parameters
Number
1 CASx pulse width
2 RASx pulse width
3 CASx asserted to RASx asserted
4 RASx negated to CASx negated
5 CASx negated to next CASx asserted
6 DWE negated before CASx asserted
Note: RASx stands for RAS0 and RAS1. CASx stands for CAS0 and CAS1.
19.3.9

DRAM Hidden Refresh Cycle (Low-Power Mode)

Figure 19-9 shows the DRAM hidden refresh cycle timing diagram for low-power mode. The signal values
and units of measure for this figure are found in Table 19-11 on page 19-13. Detailed information about
the operation of individual signals can be found in Chapter 7, "DRAM Controller."
CASx
RASx
DWE
Figure 19-9. DRAM Hidden Refresh Cycle (Low-Power Mode) Timing Diagram
19-12
1
3 2
6
Characteristic
5
1
3 4
6 2
MC68VZ328 User's Manual
5
4
(3.0 ± 0.3) V
Minimum Maximum
88 —
88 —
28 32
-28 —
88 —
58 —
Unit
ns
ns
ns
ns
ns
ns