Read-Modify-Write Accesses; Cache Filling; Single Entry Mode - Motorola MC68030 User Manual

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6.1.2.2 READ-MODIFY-WRITE ACCESSES.
The read portion of a read-modify-write
cycle is always forced to miss in the data cache. However, if the system
allows internal caching of read-modify-write cycle operands (ClOUT and CIIN
both negated), the processor either uses the data read from memory to
update a matching entry in the data cache or creates a new entry with the
read data in the case of no matching entry. The write portion of a read-
modify-write operation also updates a matching entry in the data cache. In
the case of a cache miss on the write, the allocation of a new cache entry
for the data being written is controlled by the WA bit. Table search accesses,
however, are completely ignored by the data cache; it is never updated for
a table search access.
6.1.3 Cache Filling
The bus controller can load either cache in either of two ways:
. CD
Single entry mode
o Burst fill mode
In the single entry mode, the bus controller loads a single long-word entry
of a cache line. In the burst fill mode, an entire line (four long words) can be
filled. Refer to SECTION 7 BUS OPERATION for detailed information about
the bus cycles required for both modes.
6.1.3.1 SINGLE ENTRY MODE. When a cachable access is initiated and a burst
mode operation is not requested by the MC68030 or is not supported by
external hardware, the bus controller transfers a single long word for the
corresponding cache entry. An entire long word is required. If the port size
of the responding device is smaller than 32 bits, the MC68030 executes all
bus cycles necessary to fill the long word.
6-10
When a device cannot supply its entire port width of data, regardless of the
size of the transfer, the responding device must consistently assert the cache
inhibit input (CIIN) signal. For example, a 32-bit port must always supply 32
bits, even for 8- and 16-bit transfers; a 16-bit port must supply 16 bits, even
for 8-bit transfers. The MC68030 assumes that a 32-bit termination signal for
the bus cycle indicates availability of 32 valid data bits, even if only 16 or 8
bits are requested. Similarly, the processor assumes that a 16-bit termination
signal indicates that all 16 bits are valid. If the device cannot supply its full
port width of data, it must assert CIIN for all bus cycles corresponding to a
cache entry.
MC68030 USER'S MANUAL
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