Sdram Self Refresh Entry - Motorola MPC8240 User Manual

The entry timing for self-refreshing SDRAMs is shown in Figure 6-19.
SDRAM
CLK[0:3]
CKE
CS
SDRAS
SDCAS
ADDR
WE
DQM[0:7]
DATA
The exit timing for self-refreshing SDRAMs is shown in Figure 6-20.
SDRAM
CLK[0:3]
CKE
CS
SDRAS
SDCAS
ADDR
WE
DQM[0:7]
DATA
(Tri-stated)
Figure 6-19. SDRAM Self Refresh Entry
(Tri-stated)
Figure 6-20. SDRAM Self Refresh Exit
Chapter 6. MPC8240 Memory Interface
SDRAM Interface Operation
12 cycles
A10 = 1
6-35