Pcmcia 1.0 Support; Block Diagram Overview - Motorola DragonBall MC68328 User Manual

WAIT
This field determines the number of wait states added before an internal DTACK is re-
turned for this chip-select.
000 = Zero wait states
001 = One wait state
010 = Two wait states
011 = Three wait states
100 = Four wait states
101 = Five wait states
110 = Six wait states
111 = External DTACK

2.6 PCMCIA 1.0 SUPPORT

The MC68328 processor supports PCMCIA 1.0 memory card chip-selects and read / write
signals. To meet the fanout requirement, use external buffers to interface to the memory
card.

2.6.1 Block Diagram Overview

The PCMCIA address decode is through CSD3. Selecting CSD3 assets the corresponding
PCMCIA control signals.
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
Chip Select
Decode
PCMCIA
Signal
Decode
Figure 2-13. PCMCIA Block Diagram
CSD3
CE1
CE2
OE
WE
System Integration Module
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