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waits for a restart of the channel and the negation of BEAR before starting
any new bus cycles.
NOTE
Any data that was previously read from the source into the OHR will
be lost.
3.1.7.3 HALT. IDMA transfer operation may be suspended at anytime by asserting
HAIT
to the IDMA. In response, any bus cycle in progress is completed (after
DTACK is asserted), and bus ownership is released. No further bus cycles •
will be started while HALT remains asserted. When the IDMA is in the middle
of an operand transfer when halted and HALT is subsequently negated, and
if a new transfer request is pending, then IDMA will arbitrate for the bus and
continue normal operation.
3.1.7.4 RETRY. When HALT and BERA are asserted during a bus cycle, the IDMA
terminates the bus cycle, releases the bus, and suspends any further oper-
ation until these signals are negated. When HALT and BERR are negated, the
IDMA will arbitrate for the bus, re-execute the previous bus cycle, and con-
tinue normal operation.
3.2 INTERRUPT CONTROLLER
The IMP interrupt controller accepts and prioritizes both internal and external
interrupt requests and generates a vector number during the CPU interrupt
acknowledge cycle. Interrupt nesting is also provided so that an interrupt
service routine of a lower priority interrupt may be suspended by a higher
priority interrupt request. The interrupt controller block diagram is shown in
Figure 3-2.
The on-chip interrupt controller has the following features:
• Two Operational Modes: Normal and Dedicated
• Eighteen Prioritized Interrupt Sources (Internal and External)
• A Fully Nested Interrupt Environment
• Unique Vector Number for Each Internal/External Source Generated
• Three Interrupt Request and Interrupt Acknowledge Pairs
MOTOROLA
MC68302 USER'S MANUAL
3-17
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