Post-Update By Offset N: (Rn)+N, (Sp)+N; Figure 4-6 Address Register Indirect: Post-Update By Offset N - Motorola DSP56800 Manual

16-bit digital signal processor
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4.2.2.4

Post-Update by Offset N: (Rn)+N, (SP)+N

The address of the operand is in the address register Rn or SP. After the operand address is used, the
contents of the N register are added to Rn and stored in the same address register. The content of N is
treated as a two's-complement signed number. The contents of the N register are unchanged. The type of
arithmetic (linear or modulo) used to update Rn is determined by M01 for R0 and R1 and is always linear
for R2, R3, and SP. This reference is classified as a memory reference. See Figure 4-6.
Before Execution
Y1
Y
5
5
5
31
15
$3204
X
$3200
X
R2
15
N
15
M01
15
Assembler syntax: X:(Rn)+N, X:(SP)+N, P:(Rn)+N
Additional instruction execution cycles: 0
Additional effective address program words: 0
Figure 4-6. Address Register Indirect: Post-Update by Offset N
Post-Update by Offset N Example
Y0
5
A
A
A
A
16 15
0
X Memory
0
X
X
X
X
X
X
$3200
0
$0004
0
$FFFF
0
Address Generation Unit
: MOVE Y1,X:(R2)+N
After Execution
Y1
Y
5
5
5
5
A
31
16 15
X Memory
15
$3204
X
X
X
$3200
5
5
5
R2
$3204
15
N
$0004
15
M01
$FFFF
15
Addressing Modes
Y0
A
A
A
0
0
X
5
0
0
0
AA0019
4-13

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