Address Map B Options Register-0Xe0 - Motorola MPC8240 User Manual

Integrated host processor with integrated pci
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4.9 Address Map B Options Register—0xE0
The address map B options register (AMBOR) controls various configuration settings that
can be used to alias some addresses and to control accesses to holes in the address map.
Unrelated to address map B, there is also a bit that controls the operation of the DLL. See
Section 3.3.2, "DLL Operation and Locking," for more information about operation of the
DLL.
Figure 4-28 shows the bits of the AMBOR.
DLL_RESET
PCI_FD_ALIAS_EN
CPU_FD_ALIAS_EN
Figure 4-28. Address Map B Options Register (AMBOR)—0xE0
Table 4-37 shows the specific bit settings for the AMBOR.
Table 4-37. Bit Settings for the AMBOR—0xE0
Bits
Name
7
CPU_FD_ALIAS_EN
6
PCI_FD_ALIAS_EN
5
DLL_RESET
4
0
7
6
5
4
3
Reset
Value
1
Used to direct processor accesses to addresses that begin with
0xFDxx_xxxx. This bit is used only for address map B (and not
supported in agent mode).
0 Access are routed normally
1 Processor accesses with 0xFDxx_xxxx address are forwarded to the
PCI bus as PCI memory accesses to 0x00xx_xxxx.
1
Used to direct processor responses to addresses that begin with
0xFDxx_xxxx. This bit is used only for address map B (and not
supported in agent mode).
0 No response
1 The MPC8240, as a PCI target, responds to addresses in the range
0xFD00_0000–0xFDFF_FFFF (asserts DEVSEL), and forwards the
transaction to system memory as 0x0000_0000–0x00FF_FFFF.
0
Used to reset the DLL tap point. See Section 3.3.2, "DLL Operation and
Locking." This bit must be explicitly set and then cleared by software
during initialization in order to guarantee correct operation of the DLL
and the SDRAM_CLK[0:3] signals (if they are used)
0 DLL tries to lock the phase between the SDRAM_SYNC_IN signal
and the internal sys_logic_clk signal.
1 The SDRAM_CLK signals are driven from tap point 0 of the internal
delay line.
0
Reserved
Chapter 4. Configuration Registers
Address Map B Options Register—0xE0
PCI_COMPATIBILITY_HOLE
PROC_COMPATIBILITY_HOLE
0 0
2
1
0
Description
4-41

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