Inbound And Outbound Message Registers; Inter-Integrated Circuit; Intelligent Input/Output Controller (I O); Controller - Motorola MPC8240 User Manual

Peripheral Logic Overview

1.4.6.2 Inbound and Outbound Message Registers

The MPC8240 contains two 32-bit inbound message registers and two 32-bit outbound
message registers. The inbound registers allow a remote host or PCI master to write a 32-bit
value, causing an interrupt to the processor core. The outbound registers allow the
processor core to write an outbound message which causes the outbound interrupt signal
INTA to assert.
1.4.6.3 Intelligent Input/Output Controller (I
The intelligent I/O specification is an open standard that defines an abstraction layer
interface between the OS and subsystem drivers. Messages are passed between the message
abstraction layer from one device to another.
The I O specification describes a system as being made up of host processors and
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input/output platforms (IOPs). The host processor is a single processor or a collection of
processors working together to execute a homogenous operating system. An IOP consists
of a processor, memory, and I/O interfaces. The IOP functions separately from other
processors within the system to handle system I/O functions.
The I O controller of the MU enhances communication between hosts and IOPs within a
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system. There are two paths for messages—an inbound queue is used to transfer messages
from a remote host or IOP to the processor core, and an outbound queue is used to transfer
messages from the processor core to the remote host. Each queue is implemented as a pair
of FIFOs. The inbound and outbound message queues each consists of a free_list FIFO and
a post_list FIFO.
Messages are transferred between the host and the IOP using PCI memory-mapped
registers. The MPC8240's I
inbound and outbound registers and local IOP memory. Interrupts signal the host and IOP
to indicate the arrival of new messages.
1.4.7 Inter-Integrated Circuit (I
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The I C serial interface has become an industry de facto standard for communicating with
low-speed peripherals. Typically, it is used for system management functions and
EEPROM support. The MPC8240 contains an I
functionality.

1.4.8 Embedded Programmable Interrupt Controller (EPIC)

The integrated embedded programmable interrupt controller (EPIC) of the MPC8240
reduces the overall component count in embedded applications. The EPIC unit is designed
to collect external and internal hardware interrupts, prioritize them, and deliver them to the
processor core.
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O controller facilitates moving the messages to and from the
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MPC8240 Integrated Processor User's Manual
O)
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C) Controller
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C controller with full master and slave