Interrupt Latency - Motorola MC68341 User Manual

6. Additional Notes on CPU Space Address Encoding
On page 3-31, Figure 3-16, the BKPT field for the Breakpoint Acknowledge address encoding is on bits 4-2,
and the T bit is on bit 1. The Interrupt Acknowledge LEVEL field is on bits 3-1.
7. Breakpoints
On page 3-31, the last paragraph implies that either a software breakpoint (BKPT instruction) or hardware
breakpoint can be used to insert an instruction. As noted in the following paragraphs, only a software
breakpoint can be used to insert an instruction on the breakpoint acknowledge cycle.

8. Interrupt Latency

Add to the Interrupt Acknowledge Bus Cycles section on page 3-36: Interrupt latency from IRQx assert to
prefetch of the first instruction in the interrupt handler is about 37 clocks + worst case instruction length in
clocks (using 2-clock memory and autovector termination). From the instruction timing tables, this gives 37+71
(DIVS.L with worst-case <fea>) = 108 clocks worst case interrupt latency time. For applications requiring
shorter interrupt response time the latency can be reduced by using simpler addressing modes and/or avoiding
use of longer instructions (specifically DIVS.L, DIVU.L, MUL.L).
9. Interrupt Hold Time and Spurious Interrupts
Add to the Interrupt Acknowledge Bus Cycles section on page 3-36: Level sensitive interrupts must remain
asserted until the corresponding IACK cycle; otherwise, a spurious interrupt exception may result or the inter-
rupt may be ignored entirely. This is also true for level sensitive external interrupts which are autovectored us-
ing either the AVEC signal or the AVEC register, since the SIM will not respond to an interrupt arbitration cycle
on the IMB if the external interrupt at that level has been removed. External interrupts configured as edge sen-
sitive only have to be held a minimum of 1.5 clocks - see section 4.3.5.8 PROGRAMMABLE INTERRUPT
REGISTER (PIR).
Note that the level 7 interrupt is also level sensitive, and must be held until a level 7 IACK begins. The level 7
interrupt is unique in that it cannot be masked - another level 7 interrupt exception can be created after the
IACK cycle by negating IRQ7 and reasserting, even though the interrupt mask level in the SR is now set to
level 7.
10. Typos in IACK Cycle Timing Waveforms
On page 3-38, Figure 3-21, the text "VECTOR FROM 16-BIT PORT" should be on D7-D0, and "VECTOR
FROM 8-BIT PORT" should be on D15-D8. The responding device returns the vector number on the least sig-
nificant byte of the data port.
11. Additional Note on Internal Autovector Operation
Add to the Autovector Interrupt Acknowledge Cycle section on page 3-38: If an external interrupt level is
autovectored either by the AVEC register programming or the external AVEC signal, an external IACK will be
started and terminated internally. The interrupting device should not respond to this IACK in any way, or the
resulting operation is undefined.
12. Additional Notes on Retry Termination
On page 3-42, Table 3-4: When HALT and BERR are asserted together in case #5 to force a retry of the current
bus cycle, relative timing of HALT and BERR must be controlled to avoid inadvertently causing bus error ter-
MOTOROLA MC68341 USER'S MANUAL ADDENDUM 4