Mmu Data Access Protection Register - Motorola MPC823e Reference Manual

Memory Management Unit
11.6.1.9 MMU DATA ACCESS PROTECTION REGISTER. The MMU data access
protection (MD_AP) register contains the access protection group for the data memory
management unit.
MD_AP
BIT 0 1 2
FIELD GP0 GP1
RESET — —
R/W R/W R/W
ADDR
BIT 16 17 18
FIELD GP8 GP9
RESET — —
R/W R/W R/W
ADDR
NOTE: — = Undefined.
GPx—Group Protection
In domain manager mode, these bits have the following settings.
00 = No access.
01 = Client-access permission defined by page protection bits.
10 = Reserved.
11 = Manager-free access.
In PowerPC mode, the GPx bits have these settings and are privilege and problem state
(Ks and Kp) in the PowerPC Microprocessor Family: The Programming Environment for
32-Bit Microprocessors manual:
00 = All accesses are considered privileged.
01 = Access permission defined by page protection bits.
10 = Problem and privileged interpretation is swapped.
11 = All accesses are considered problem.
11-32
3 4 5 6 7
GP2 GP3
— —
R/W R/W
SPR 794
19 20 21 22 23
GP10 GP11
— —
R/W R/W
SPR 794
MPC823e REFERENCE MANUAL
8 9 10 11 12
GP4 GP5 GP6
— — —
R/W R/W R/W
24 25 26 27 28
GP12 GP13 GP14
— — —
R/W R/W R/W
13 14 15
GP7
—
R/W
29 30 31
GP15
—
R/W
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