ST STM32G4 Series Reference Manual page 1489

RM0440
Bit 0 CCF: Computation completed flag
This flag indicates whether the computation is completed:
0: Not completed
1: Completed
The flag is set by hardware upon the completion of the computation. It is cleared by software, upon
setting the CCFC bit of the AES_CR register.
Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the AES_CR
register.
The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1.
33.7.3 AES data input register (AES_DINR)
Address offset: 0x08
Reset value: 0x0000 0000
Only 32-bit access type is supported.
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Bits 31:0 DIN[x+31:x]: One of four 32-bit words of a 128-bit input data block being written into the peripheral
This bitfield feeds a 32-bit input buffer. A 4-fold sequential write to this bitfield during the input phase
virtually writes a complete 128-bit block of input data to the AES peripheral. Upon each write, the
data from the input buffer are handled by the data swap block according to the DATATYPE[1:0]
bitfield, then written into the AES core 128-bit input buffer.
The substitution for "x", from the first to the fourth write operation, is: 96, 64, 32, and 0. In other
words, data from the first to the fourth write operation are: DIN[127:96], DIN[95:64], DIN[63:32], and
DIN[31:0].
The data signification of the input data block depends on the AES operating mode:
- Mode 1 (encryption): plaintext
- Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for input)
- Mode 3 (decryption) and Mode 4 (key derivation then single decryption): ciphertext
The data swap operation is described in
page 1477.
27 26 25 24
DIN[x+31:x+16]
rw rw rw rw
11 10 9 8
rw rw rw rw
RM0440 Rev 1
23 22 21
rw rw rw
7 6 5
DIN[x+15:x]
rw rw rw
Section 33.4.13: AES data registers and data swapping on
AES hardware accelerator (AES)
20 19 18
rw rw rw
4 3 2
rw rw rw
17 16
rw rw
1 0
rw rw
1489/2083
1497