ST STM32G4 Series Reference Manual page 1488

Advanced arm-based 32-bit mcus

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AES hardware accelerator (AES)

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 BUSY: Busy

This flag indicates whether AES is idle or busy during GCM payload encryption phase:

The flag is controlled by hardware. When the flag indicates "idle", the current message processing

may be suspended to process a higher-priority message.

This flag is effective only in GCM payload encryption phase. in other chaining modes, or in GCM

phases other than payload encryption, the flag must be ignored.

Bit 2 WRERR: Write error

This flag indicates the detection of an unexpected write operation to the AES_DINR register (during

computation or data output phase):

0: Not detected

The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR

Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR

The flag setting has no impact on the AES operation.

The flag is not effective when key derivation mode, or GCM/CCM Init phase is selected.

Bit 1 RDERR: Read error flag

This flag indicates the detection of an unexpected read operation from the AES_DOUTR register

(during computation or data input phase):

0: Not detected

The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR

Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR

The flag setting has no impact on the AES operation.

The flag is not effective when key derivation mode, nor GCM/CCM init/header phase is selected.

RM0440 Rev 1

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