ST STM32G4 Series Reference Manual page 1504

Advanced arm-based 32-bit mcus
Hide thumbs Also See for STM32G4 Series:
Table of Contents

Advertisement

Real-time clock (RTC)
A programmable prescaler stage generates a 1 Hz clock which is used to update the
calendar. To minimize power consumption, the prescaler is split into 2 programmable
prescalers (see
A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the
RTC_PRER register.
A 15-bit synchronous prescaler configured through the PREDIV_S bits of the
RTC_PRER register.
Note:
When both prescalers are used, it is recommended to configure the asynchronous prescaler
to a high value to minimize consumption.
The asynchronous prescaler division factor is set to 128, and the synchronous division
factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency
of 32.768 kHz.
The minimum division factor is 1 and the maximum division factor is 2
This corresponds to a maximum input frequency of around 4 MHz.
f
is given by the following formula:
ck_apre
The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it
reaches 0, RTC_SSR is reloaded with the content of PREDIV_S.
f
is given by the following formula:
ck_spre
The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit
wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload
timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous
prescaler (see
34.3.5
Real-time clock and calendar
The RTC calendar time and date registers are accessed through shadow registers which
are synchronized with PCLK (APB clock). They can also be accessed directly in order to
avoid waiting for the synchronization duration.
RTC_SSR for the subseconds
RTC_TR for the time
RTC_DR for the date
Every RTCCLK periods, the current calendar value is copied into the shadow registers, and
the RSF bit of RTC_ICSR register is set (see
(RTC_SHIFTR)). The copy is not performed in Stop and Standby mode. When exiting these
modes, the shadow registers are updated after up to 4 RTCCLK periods.
When the application reads the calendar registers, it accesses the content of the shadow
registers. It is possible to make a direct access to the calendar registers by setting the
1504/2083
Figure 527: RTC block
f
CK_APRE
-----------------------------------------------------------------------------------------------
f
=
CK_SPRE
(
PREDIV_S
Section 34.3.7: Periodic auto-wakeup
RM0440 Rev 1
diagram):
f
RTCCLK
-------------------------------------- -
=
PREDIV_A
+
1
f
RTCCLK
1
)
×
(
PREDIV_A
+
for details).
Section 34.6.10: RTC shift control register
RM0440
22
.
1
)
+

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the STM32G4 Series and is the answer not in the manual?

Questions and answers

Table of Contents

Save PDF