Loop Mode Instruction Execution; Vector Base Register - Motorola CPU32 Reference Manual

1.1.2 Loop Mode Instruction Execution
The CPU32 has several features that provide efficient execution of program
loops. One of these features is the DBcc looping primitive. To increase the
performance of the CPU32, a loop mode has been added to the processor. The
loop mode is used by any single-word instruction that does not change the
program flow. Loop mode is implemented in conjunction with the DBcc
instruction. Figure 1-1 shows the required form of an instruction loop for the
processor to enter loop mode.
Loop mode is entered when DBcc is executed and loop displacement is -4.
Once in loop mode, the processor performs only data cycles associated with the
instruction and suppresses instruction fetches. Termination condition and count
are checked after each execution of looped instruction data operations. The
CPU automatically exits loop mode for interrupts or other exceptions.
ONE-WORD INSTRUCTION
~
DSce
OSee DISPLACEMENT
r - -
$FFFC=-4
Figure 1-1. Loop Mode Instruction Sequence
1.1.3 Vector Base Register
The vector base register (VBR) contains the base address of the 1024-byte
exception vector table. The table contains 256 exception vectors. Exception
vectors are the memory addresses of routines that begin execution at the
completion of exception processing. Each routine performs operations
appropriate to the corresponding exception. Because exception vectors are
memory addresses, each table entry is a single long word.
Each vector is assigned an 8-bit number. Vector numbers for some exceptions
are obtained from an external device; others are supplied automatically by the
processor. The processor multiplies the vector number by four to calculate
vector offset, then adds the offset to the VBR base
addre~s.
The sum is the
memory address of the vector.
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