Spi 1 Programming Model; Spi 1 Receive Data Register; Table 13-1 Spi 1 Receive Data Register Description - Motorola MC68VZ328 User Manual

SPI 1 Programming Model

13.3 SPI 1 Programming Model
This section provides information for programming SPI 1.
13.3.1

SPI 1 Receive Data Register

This read-only register holds the top of the 8
device during data transaction. The bit position assignments for this register are shown in the following
register display. The settings for this register are described in Table 13-1.
SPIRXD
BIT 7
TYPE r
0
RESET
Name
DATA Data—Top of SPI 1's RxFIFO (8 × 16)
Bits 7–0
13-4
×
16 RxFIFO, which receives data from an external SPI
SPI 1 Receive Data Register
6 5
r r
0 0
Table 13-1. SPI 1 Receive Data Register Description
Description
MC68VZ328 User's Manual
4 3 2
DATA
r r r
0 0 0
0x0000
Setting
The data in this register has no meaning if the RR bit
in the interrupt control/status register is cleared.
0x(FF)FFF700
1 BIT 0
r r
0 0