Table 7-9 Sdram Bank Address Programming Examples - Motorola MC68VZ328 User Manual

Table 7-8. SDRAM Control Register Description (Continued)
Name
BNKADDL SDRAM Low Order Bank Address Line
Bits 3–2 Selection—A 2-bit bank register selection address is
generated by selecting the appropriate CPU address
line. This register bit allows selection of the low order
bit.
CL CAS Latency—This bit selects the CAS latency for the
Bit 1 SDRAM cycle. The bit must be programmed before the
initialization sequence.
RACL Refresh to Active Command Latency—This bit
Bit 0 selects the latency for SDRAM from refresh to active
cycle.
Table 7-9. SDRAM Bank Address Programming Examples
Application
Make all SDRAM appear as one
single bank
Two banks of SDRAM—for exam-
ple, 16 Mbyte
Four banks of SDRAM—for
example, 64 Mbyte
Four banks of SDRAM—for
example, 128 Mbyte
Four banks of SDRAM—for
example, 256 Mbyte
Note: These bits are all set in EDO RAM or Fast Page Mode, allowing the use of only one page register.
Description
BNKADDH BNKADDL
11 11
00 11
01 10
01 10
10 10
DRAM Controller
Programming Model
Setting
00 = PA19.
01 = PA21.
10 = PA23.
11 = Force this bank address line to 0.
See Table 7-9 for programming examples.
0 = CAS latency is 1 clock count.
1 = CAS latency is 2 clock counts.
0 = 3 Clock counts.
1 = 6 Clock counts.
Remarks
None
Choose PA20 as bank selection address
Choose PA22 and PA21 as bank selection
address
Choose PA22 and PA23 as bank selection
address
Choose PA24 and PA23 as bank selection
address
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