Memory Bank Enable Register-0Xa0 - Motorola MPC8240 User Manual

Table 4-23. Bit Settings for Extended Memory Ending Address Registers 1 and 2
Bits Name
31–26 —
25–24 Extended ending address 7
23–18 —
17–16 Extended ending address 6
15–10 —
9–8 Extended ending address 5
7–2 —
1–0 Extended ending address 4
4.6.2 Memory Bank Enable Register—0xA0
Individual banks of memory are enabled or disabled by using the 1-byte memory bank
enable register, shown in Figure 4-15 and Table 4-24. Each enabled memory bank
corresponds to a physical bank of memory enabled by one of the RAS[0:7] signals (for
DRAM/EDO) or one of the CS[0:7] signals (for SDRAM). If a bank is enabled, the ending
address of that bank must be greater than or equal to its starting address. If a bank is
disabled, no memory transactions access that bank regardless of its starting and ending
addresses.
Figure 4-15. Memory Bank Enable Register—0xA0
Table 4-24. Bit Settings for Memory Bank Enable Register—0xA0
Reset
Value
All 0s
0b00
All 0s
0b00
All 0s
0b00
All 0s
0b00
Bank 4
Bank 5
Bank 6
Bank 7
7 6
Reset
Bits Name
Value
7 Bank 7
6 Bank 6
Chapter 4. Configuration Registers
Memory Interface Configuration Registers
Description
Reserved
Extended ending address for bank 7
Reserved
Extended ending address for bank 6
Reserved
Extended ending address for bank 5
Reserved
Extended ending address for bank 4
5 4 3 2 1 0
Description
0 Bank 7
0 Disabled
1 Enabled
0 Bank 6
0 Disabled
1 Enabled
Byte Address
0x9C
Bank 3
Bank 2
Bank 1
Bank 0
4-27