Programmable Data-Bus Size - Motorola DragonBall MC68328 User Manual

System Integration Module
mination signal (DTACK) with a programmable number of wait states. This feature elimi-
nates board space that would otherwise be necessary for cycle-termination logic.
The 16 general-purpose chip-selects allow up to 4 different classes of devices/memory for
use in a system without external decode or wait-state generation logic. For example, to
address a 16 Mbyte ROM space, 4 pairs of 16-Mbit ROM chips are used (CSA0 through
CSA3 are connected to those 4 pairs of ROMs). Another typical configuration could be an
8-bit EPROM, a fast 16-bit SRAM, up to 4 simple I/O peripherals, and a nonvolatile flash
memory.
The chip-select block diagram is shown in Figure 2-2.
The basic chip-select model allows the chip-select output signal to assert in response to an
address match. The signals are asserted externally shortly after AS goes low. The address
match is described in terms of a base address and an address mask. Thus, the byte size of
the matching block must be a power of 2, and the base address must be an integer multiple
of this size. Therefore, an 8-Kbyte block size must begin on an 8-Kbyte boundary, and a 64-
Kbyte block size can only begin on a 64-Kbyte boundary, etc.
Each chip-select is programmable and the registers have read-write capability so that the
values programmed can be read back.
For a given chip-select, users may also choose: (1) whether the chip-select allows read-only
or read/write accesses, (2) whether a DTACK is automatically generated for this chip-select,
and (3) the number of wait states (from zero to six).
2.1.2.1 PROGRAMMABLE DATA-BUS SIZE. Each of the chip-selects includes the facility
of a data-bus port-sizing extension to the basic M68000 bus. This allows the system
designer to mix 16-bit and 8-bit contiguous address memory devices (RAM, ROM) on a 16-
bit data-bus system. If the CPU core performs a 16-bit data transfer in an 8-bit memory
space, then two 8-bit cycles will occur. However, the address strobe and data strobe remain
asserted until the end of the second 8-bit cycle. In this case, only the external MC68EC000
data bus upper byte (D15-D8) is used; the least significant bit of address (A0) increments
automatically from one to the next. A0 should be ignored in 16-bit data-bus cycles even if
only the upper or lower byte is being read/written.
Note that a 16-bit data bus is always used internally for access to peripheral registers,
regardless of any mode settings for the external bus. Where internal peripheral registers are
16-bits wide, they can be read or written only in one bus cycle. This eliminates possible con-
flicts and reading of inaccurate values where 16-bit-wide register contents are volatile (timer
counter registers, for example) or where the whole 16-bit value affects some aspect of sys-
tem operation (chip-select base address, for example).
It is recommended that any external peripheral that needs only an 8-bit data-bus interface
but does not require contiguous address locations: (1) use a chip-select configured as 16-
bit data-bus width, and (2) connect to D7-D0. This balances more evenly the load on the two
halves of the data bus in an 8-bit system.
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL 2-3