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FRZ—Freeze Activity
The FRZ pin is used to freeze the activity of selected peripherals. This is useful for system
debugging purposes. Refer to 3.8 System Control for more details on which peripherals
are affected. FRZ should be continuously negated during total system reset.
5.5 ADDRESS BUS PINS (A23–A1)
The address bus pins are shown in Figure 5-4.
A23—A1 form a 24-bit address bus when combined with UDS/A0. The address bus is a bi-
directional, three-state bus capable of addressing 16M bytes of data (including the IMP in-
ternal address space). It provides the address for bus operation during all cycles except
CPU space cycles. In CPU space cycles, the CPU reads a peripheral device vector number.
These lines are outputs when the IMP (M68000 core, SDMA or IDMA) is the bus master and
are inputs otherwise.
5.6 DATA BUS PINS (D15—D0)
The data bus pins are shown in Figure 5-5.
This 16-bit, bidirectional, three-state bus is the general-purpose data path. It can transmit
and accept data in either word or byte lengths. For all 16-bit IMP accesses, byte 0, the high-
order byte of a word, is available on D15–D8, conforming to the standard M68000 format.
MOTOROLA
MC68302
Figure 5-4. Address Bus Pins
MC68302
Figure 5-5. Data Bus Pins
MC68302 USER'S MANUAL
A23–A1
A23–A1
Signal Description
5-7
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