Table 7-4 Dsp56800 Core Reset And Interrupt Vector Table - Motorola DSP56800 Manual

Steps 1 through 3 listed on page page 7-5 require two additional instruction cycles, effectively making the
interrupt pipeline five levels deep.
7.3.2 Reset and Interrupt Vector Table
The interrupt vector table specifies the addresses that the processor accesses once it recognizes an interrupt
and begins exception processing. Since peripherals can also generate interrupts, the interrupt vector map
for a given chip is specified by all sources on the DSP core as well as all peripherals that can generate an
interrupt. Table 7-4 lists the reset and interrupt vectors available on DSP56800-based DSP chips. The
interrupt vectors used by on-chip peripherals, or by additional device-specific interrupt will be listed in the
user's manual for that chip.
Table 7-4. DSP56800 Core Reset and Interrupt Vector Table
Interrupt
Interrupt
Starting
Priority Level
Address
$0000
$0002
$0004
$0006
$0008
$000A
$000C
$000E
$0010
$0012
$0014
$0016
$0018
$001A
$001C
$001E
$0020
$007C
$007E
-
-
-
1
1
1
1
1
0
0
0 (Vector Available for On-Chip Peripherals)
0 (Vector Available for On-Chip Peripherals)
0 (Vector Available for On-Chip Peripherals)
0 (Vector Available for On-Chip Peripherals)
0 (Vector Available for On-Chip Peripherals)
0 (Vector Available for On-Chip Peripherals)
0 (Vector Available for On-Chip Peripherals)
0 (Vector Available for On-Chip Peripherals)
0 (Vector Available for On-Chip Peripherals)
Interrupts and the Processing States
Exception Processing State
Interrupt Source
Hardware Reset
COP Watchdog Reset
(Reserved)
Illegal Instruction Trap
SWI
Hardware Stack Overflow
OnCE Trap
(Reserved)
IRQA
IRQB
...
7-7