Processor Version Register (Pvr); Powerpc Instruction Set And Addressing Modes; Calculating Effective Addresses; Powerpc Instruction Set - Motorola MPC8260 PowerQUICC II User Manual

Part I. Overview

2.3.1.2.4 Processor Version Register (PVR)

Software can identify the MPC8260Õs processor core by reading the processor version
register (PVR). The MPC8260Õs processor version number is 0x0081; the processor
revision level starts at 0x0100 and is incremented for each revision of the chip.

2.3.2 PowerPC Instruction Set and Addressing Modes

All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats
are consistent among all instruction types, permitting efÞcient decoding to occur in parallel
with operand accesses. This Þxed instruction length and consistent format greatly simpliÞes
instruction pipelining.

2.3.2.1 Calculating Effective Addresses

The effective address (EA) is the 32-bit address computed by the processor when executing
a memory access or branch instruction or when fetching the next sequential instruction.
The PowerPC architecture supports two simple memory addressing modes:
¥ EA = (rA|0) + offset (including offset = 0) (register indirect with immediate index)
¥ EA = (rA|0) + rB (register indirect with index)
These simple addressing modes allow efÞcient address generation for memory accesses.
Calculation of the effective address for aligned transfers occurs in a single clock cycle.
For a memory access instruction, if the sum of the effective address and the operand length
exceeds the maximum effective address, the memory operand is considered to wrap around
from the maximum effective address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit unsigned
binary arithmetic. A carry from bit 0 is ignored in 32-bit implementations.
In addition to the functionality of the MPC603e, the MPC8260 has additional hardware
support for misaligned little-endian accesses. Except for string/multiple load and store
instructions, little-endian load/store accesses not on a word boundary generate exceptions
under the same circumstances as big-endian requests.

2.3.2.2 PowerPC Instruction Set

The PowerPC instructions are divided into the following categories:
¥ Integer instructionsÑThese include arithmetic and logical instructions.
Ñ Integer arithmetic
Ñ Integer compare
Ñ Integer logical
Ñ Integer rotate and shift
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