Burst Data Transfers - Motorola DigitalDNA ColdFire MCF5272 User Manual

Burst Data Transfers

20.7 Burst Data Transfers
The MCF5272 uses line read transfers to access 16 bytes to support cache line fillingDMA
transfers, and MOVEM instructions, when appropriate. A cache line read accesses a block
of four longwords, aligned to a longword memory boundary, by supplying a starting
address that points to one of the longwords and incrementing A[3:0] of the supplied address
for each transfer. A longword read accesses a single longword aligned to a longword
boundary and increments A1 and A0 if the accessed port size is smaller than 32 bits. A word
read accesses a single word of data, aligned to a word boundary and increments A0 if the
accessed port size is smaller than 16 bits.
The MCF5272 uses line write transfers to access a 16-byte operand for MOVEM
instructions and DMA transfers, when appropriate. A line write accesses a block of four
longwords, aligned to a longword memory boundary, by supplying a starting address that
points to one of the longwords and increments A[3:0] of the supplied address for each
transfer. A longword write accesses a single longword aligned to a longword boundary and
increments A1 and A0 if the accessed port size is smaller than 32 bits. A word write
accesses a single word of data, aligned to a word boundary and increments A0 if the
accessed port size is smaller than 16 bits.
The MCF5272 hardware supports the following types of burst transfers.
• Sixteen byte cache line read bursts from 32-bit wide SDRAM with access times of
n-1-1-1. The value of n depends on read, write, page miss, page hit, etc. See
Chapter 9, "SDRAM Controller," for complete details of access times. To enable
this type of transfer, CSOR7[EXTBURST] must be cleared, CSBR7[EBI] must be
01, and CSBR7[BW] must be 11.
• Sixteen byte cache line read bursts from 16-bit wide SDRAM with access times of
n-1-1-1-1-1-1-1. CSOR7[EXTBURST] must be set, CSBR7[EBI] must be 01, and
CSBR7[BW] must be 10.
• Sixteen byte read or write bursts during Ethernet DMA transfers to/from SDRAM
with access times of n-1-1-1 or n-1-1-1-1-1-1-1 depending on 32 or 16 bit SDRAM
port width as described in the previous two paragraphs.
All bursts to and from SRAM or from ROM appear as a sequence of four single longword
accesses in the case of 32-bit wide memory. In the case of 16-bit wide SRAM or ROM
memory, a burst appears as a sequence of eight single word accesses. In the case of 8 bit
wide SRAM or ROM memory a burst appears as a sequence of sixteen single byte accesses.
It is never necessary to set CSORn[EXTBURST] when CSORn[EBI] = 00 or 11.
CSBRn[BW] = 11 is invalid for SRAM/ROM; it should be programmed with the port size.
20.8 Misaligned Operands
All MCF5272 data formats can be located in memory on any byte boundary. A byte operand
is properly aligned at any address; a word operand is misaligned at an odd address; and a
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