Dram Bank Configuration Register (Low Half) - Motorola MC68306 User Manual

5.2.7.3 DRAM BANK CONFIGURATION REGISTER (LOW HALF)

FFFFFFE6/7 (DR1), FFFFFFE2/3 (DR0)
15 14 13 12
DRR DRFC DRFC —
6 5
RESE
T:
U U U
U
DRR—DRAM Read
This bit determines whether read cycles are permitted to DRAM bank space. If read and
write cycles are both inhibited, DRAM bank is inhibited.
0 = Read cycles are inhibited to DRAM bank space
1 = Read cycles are permitted to DRAM bank space
DRFC6, 5, 2, 1—DRAM Bank Function Code 6, 5, 2, 1 Enable
This bit determines which function code accesses are permitted to DRAM bank space. If
all function code cycles are inhibited, the DRAM bank is inhibited.
0 = Function code n cycles are inhibited to DRAM bank space
1 = Function code n cycles are permitted to DRAM bank space
DRM3–0—DRAM Bank Address Match
This field determines which DRAM bank address bits must match address bits for
DRAM bank to occur. DRA bits not included in match must be set to zero, or else
DRAM bank is inhibited.
0000 = A31–A17 ignored in DRAM bank address match
0001 = A31 must match DRA31; A30–A17 ignored in DRAM bank address match
0010 = A31–A30 must match DRA31–DRA30; A29–A17 ignored in DRAM bank
address match
.....
1111 = A31–A17 must match DRA31–DRA17 in DRAM bank address match
Table 5-4 shows the entire range of address bits that must match for a DRAM bank to
occur.
MOTOROLA
11 10 9 8
— DRFC DRFC —
2 1
U U U U
MC68306 USER'S MANUAL
7 6 5
DRM3 DRM2 DRM1 DRM0
U U U
4 3 2 1
DRSZ2 DRSZ1 DRSZ
0
U U U U
SUPERVISOR ONLY
0
DRDT
U
5- 15