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DMA request multiplexer (DMAMUX)
14.6.6
DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR)
Address offset: 0x144
Reset value: 0x0000 0000
This register must be written at bit level by a non-secure or secure write, according to the
secure mode of the considered DMAMUX request line multiplexer channel y it is assigned
to, and considering that the DMAMUX request generator x channel output is selected by the
y channel of the DMAMUX request line channel (refer to
DMAMUX_CyCR.DMAREQ_ID[7:0] and to the DMAMXUX mapping implementation
section).
This register must be written at bit level by an unprivileged or privileged write, according to
the privileged mode of the considered DMAMUX request line multiplexer channel y it is
assigned to, and considering that the DMAMUX request generator x channel output is
selected by the y channel of the DMAMUX request line channel (refer to
DMAMUX_CyCR.DMAREQ_ID[7:0] and to the DMAMXUX mapping implementation
section).
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 COF[3:0]: Clear trigger overrun event flag
Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR
register.
496/1450
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0453 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
COF3
COF2
w
w
RM0453
17
16
Res.
Res.
1
0
COF1
COF0
w
w
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