STMicroelectronics STM32WL5 Series Reference Manual page 152

Embedded flash memory (FLASH)
Bits 22:18 SBRSA[4:0]: secure "backup" SRAM2 start address
Bits 17:16 Reserved, must be kept at reset value.
Bits 15:0 SBRV[15:0]: CPU2 boot reset vector
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This bit is write protected when HDPAD = 0 and HDPADIS = 1.
When FSD = BRSD =0, SRAM2 is secure. SBRSA[4:0] contains the start address of the
first 1-Kbyte page of the secure backup SRAM2 area.
0x00: "backup" SRAM2 start address offset 0x0000 0000
0x01: "backup" SRAM2 start address offset 0x0000 0400
...
0x1F: "backup" SRAM2 start address offset 0x0000 7C00
This bit can only be accessed by software when C2BOOT_LOCK = 0
Contains the word (4 bytes) aligned CPU2 boot reset start address offset within the selected
memory area by C2OPT.
0x0000: CPU2 boot address offset 0x0000 0000
0x0001: CPU2 boot address offset 0x0000 0004
...
0x1FFF: CPU2 boot address offset 0x0000 7FFC
....
0xFFFF: CPU2 boot address offset 0x0003 FFFC
RM0453 Rev 5
RM0453